1. Technical Field
The present invention relates to a method of designing a pattern.
2. Related Art
Conventionally, there has been used a method of designing a layout, in which hole patterns for a semiconductor integrated circuit are arranged on lattice points of an orthogonally crossing virtual grid. The following advantages may be obtained by the above configuration in which the hole patterns are arranged on the lattice points of a virtual grid.
A first advantage is that the method is adoptable to an automatic interconnect arrangement tool using computer aided design (CAD). In the CAD executing processing according to a program stored beforehand, interconnects may be easily arranged as a circuit design by arranging cells, interconnect patterns, and the hole patterns on lattice points defined according to the circuit design.
A second advantage is that photolithography may be preferably performed. By arranging the hole patterns at the lattice points, which are intersections of the virtual grid of equal interval, so as to form array when arranging the hole patterns, the hole patterns with a size and a shape in conformity to a target may be easily processed onto a photoresist by utilizing interference of lights from adjacent hole patterns in an exposure process. Moreover, another advantage is that a correction form may be easily generated in optical proximity correction (OPC) only by arranging the hole patterns on the lattice points of the virtual grid without arranging the patterns in an array.
Japanese Laid-Open Patent Publication No. 2005-189683 has disclosed a technique in which a grid of interval smaller than a minimum permissible pitch according to a design rule for a semiconductor integrated circuit is provided in a pattern drawing to arrange hole patterns on lattice points which are intersections of the grid.
And, Japanese Laid-Open Patent Publication No. 2005-183793 has disclosed a method of designing a layout, in which hole patterns are arranged on lattice points, which are intersections of an orthogonally crossing virtual grid, and other hole patterns are not arranged on an adjacent lattice point which is a lattice point nearest to the lattice point, on which a hole pattern is arranged. Here, it has been considered that the size of a virtual grid may be smaller than a resolution pitch limit of a hole pattern in an exposure process for a semiconductor integrated circuit.
By configuring the virtual grid with a size smaller than a minimum permissible pitch (resolution pitch limit) according to a design rule, flexibility in arrangement of the hole patterns may be improved. Thereby, the circuit pattern area may be reduced.
However, the inventor has found a phenomenon in which, in a case in which the size of a virtual grid is smaller than a resolution pitch limit as described above, and a number of hole patterns in a certain area is increased, a dimensional error becomes larger when a reticle pattern is lithographed onto a resist pattern.